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a sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc ? processors adsp-21367/adsp-21368/adsp-21369 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bit floating point processor optimized for high performance audio processing single-instruction, multiple -data (simd) computational architecture on-chip memory2m bit of on-chip sram and 6m bit of on- chip mask programmable rom code compatible with all othe r members of the sharc family the adsp-21367/adsp-21368/adsp-21369 are available with a 333 mhz core instruction rate with unique audiocen- tric peripherals such as the digital audio interface, s/pdif transceiver, serial ports, 8-channel asynchronous sample rate converter, precision cloc k generators, and more. for complete ordering information, see ordering guide on page 56 . figure 1. function al block diagram spi port (2) timers (3) two wire interface uart (2) dpi routing unit digital peripheral interface gpio flags/ irq/timexp 4 serial ports (8) input data port/ pdap dai routing unit spdif (rx/tx) digital audio interface iod(32) addr data ioa(24) 4 block of on-chip memory pm data bus dm data bus 32 pm address bus dm address bus 64 px register processing element (pey) timer instruction cache 32 48-bit dag1 8 4 32 program sequencer dma controller 34 channels s memory-to- memory dma (2) iop register (memory mapped) control, status, & data buffers jtag test & emulation i/o processor dai pins dpi pins 64 32 14 20 src (8 channels) precision clock generators (4) 24 18 sdram controller address control 3 7 asynchronous memory interface shared memory interface 8 external port control pins pwm 32 data flags4-15 core processor dag2 8 4 32 processing element (pex) 2m bit ram 6m bit rom
rev. a | page 2 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 key featuresprocessor core at 333 mhz (3 ns) core instruction rate, the processors per- form 2 gflops/666 mmacs 2m bit on-chip, sram (0.75m bit in blocks 0 and 1, and 0.25m bit in blocks 2 and 3) for simultaneous access by the core processor and dma 6m bit on-chip, mask-programmable rom (3m bit in block 0 and 3m bit in block 1) dual data address generators (dags) with modulo and bit- reverse addressing zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing single-instruction, multiple-data (simd) architecture provides: two computational processing elements concurrent execution code compatibility with othe r sharc family members at the assembly level parallelism in buses and computational units allows: single cycle executions (with or wi thout simd) of a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at a sustained 6.4g bytes/s bandwidth at 333 mhz core instruction rate input/output features dma controller supports: 34 zero-overhead dma channels for transfers between internal memory and a variety of peripherals 32-bit dma transfers at peripheral clock speed, in parallel with full-speed processor execution 32-bit wide external port provides glueless connection to both synchronous (sdram) and asynchronous memory devices programmable wait state options: 2 sclk to 31 sclk cycles delay-line dma engine maintains circular buffers in exter- nal memory with tap/offset-based reads sdram accesses at 133 mhz and asynchronous accesses at 66 mhz shared-memory support allows multiple dsps to automat- ically arbitrate for the bus and gluelessly access a common memory device shared memory interface (adsp-21368 only) support provides: glueless connection for scalable dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus connect of up to four adsp-21368 processors and global memory four memory select lines allow multiple external memory devices digital audio interface (dai) includes eight serial ports, four precision clock generators, an input data port, an s/pdif transceiver, an 8-channel asyn chronous sample rate con- verter, and a signal routing unit digital peripheral interface (dpi) includes three timers, two uarts, two spi ports, and a two wire interface port outputs of pcg's c and d can be driven on to dpi pins eight dual data line serial ports that operate at up to 50m bits/s on each data lineeach has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair tdm support for telecommunications interfaces including 128 tdm channel support for newer telephony interfaces such as h.100/h.110 up to 16 tdm stream support, each with 128 channels per frame companding selection on a per channel basis in tdm mode input data port, configurable as eight channels of serial data or seven channels of serial data and up to a 20-bit wide parallel data channel signal routing unit provides configurable and flexible con- nections between all dai/dpi components 2 muxed flag/irq lines 1 muxed flag/timer expired line /ms pin 1 muxed flag/irq /ms pin dedicated audio components s/pdif-compatible digital audio receiver/transmitter sup- ports eiaj cp-340 (cp-1201), iec-958, aes/ebu standards left-justified, i 2 s, or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter) four independent asynchronous sample rate converters (src). each converter has separate serial input and output ports, a de-emphasis filter providing up to C140 db snr performance, stereo sample rate converter (src) and sup- ports left-justified, i 2 s, tdm, and right-justified modes and 24, 20, 18, and 16 audio data word lengths pulse-width modulation provides: 16 pwm outputs configured as four groups of four outputs supports center-aligned or edge-aligned pwm waveforms rom-based security features include: jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software and hardware multi- plier/divider ratios dual voltage: 3.3 v i/o, 1.2 v or 1.3 v core available in 256-ball sbga and 208-lead mqfp packages (see ordering guide on page 56 )
adsp-21367/adsp-21368/adsp-21369 rev. a | page 3 of 56 | august 2006 table of contents summary ................................................................1 key featuresprocessor core ..................................2 input/output features ............................................2 dedicated audio components ..................................2 general description ..................................................4 core architecture ..................................................4 memory architecture .............................................5 external memory ...................................................5 input/output features ............................................7 system design .......................................................9 development tools .............................................. 10 additional information ......................................... 11 pin function descriptions ........................................ 12 data modes ........................................................ 15 boot modes ........................................................ 15 core instruction rate to clkin ratio modes ............. 15 specifications ......................................................... 16 operating conditions ........................................... 16 electrical characteristics ........................................ 17 package information ............................................ 18 maximum power dissipation ................................. 18 absolute maximum ratings ................................... 18 esd sensitivity .................................................... 18 timing specifications ........................................... 19 output drive currents .......................................... 47 test conditions ................................................... 47 capacitive loading ............................................... 47 thermal characteristics ........................................ 48 256-ball sbga pinout .. ............................................ 49 208-lead mqfp pinout ............................................ 52 package dimensions ................................................ 54 surface-mount design .......................................... 55 ordering guide ...................................................... 56
rev. a | page 4 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 general description the adsp-21367/adsp-21368/adsp-21369 sharc proces- sors are members of the simd sharc family of dsps that feature analog devices super harvard architecture. these pro- cessors are source code-compati ble with the adsp-2126x and adsp-2116x dsps as well as with first generation adsp-2106x sharc processors in sisd (single-instruction, single-data) mode. the processors are 32-bit/40- bit floating point processors optimized for high performance automotive audio applications with its large on-chip sram, and mask-programmable rom, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital audio interface (dai). as shown in the functional block diagram on page 1 , the processors use two computational units to deliver a significant performance increase over the pr evious sharc processors on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, cmos process, the adsp-21367/adsp-21368/ adsp-21369 processors achieve an instruction cycle time of up to 3.0 ns at 333 mhz. with it s simd computational hardware, the processors can perform tw o gflops running at 333 mhz. table 1 shows performance benchmarks for these devices. the adsp-21367/adsp-21368/adsp-21369 continues sharcs industry-leading standards of integration for dsps, combining a high performance 32- bit dsp core with integrated, on-chip system features. the block diagram of the adsp-21368 on page 1 , illustrates the following architec tural features: ? two processing elements, each of which comprises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle ? three programmable interval timers with pwm genera- tion, pwm capture/pulse width measurement, and external event counter capabilities ?on-chip sram (2m bit) ?on-chip mask-progr ammable rom (6m bit) ? jtag test access port the block diagram of the adsp-21368 on page 1 also illustrates the following architectural features: ? dma controller ? eight full-duplex serial ports ? digital audio interface that includes four precision clock generators (pcg), an input da ta port (idp), an s/pdif receiver/transmitter, eight ch annels asynchronous sample rate converters, eight serial ports, eight serial interfaces, a 16-bit parallel input port (pdap) , a flexible signal routing unit (dai sru). ? digital peripheral interface that includes three timers, an i 2 c ? interface, two uarts, two serial peripheral interfaces (spi), and a flexible signal routing unit (dpi sru). core architecture the adsp-21367/adsp-21368/adsp -21369 are code compati- ble at the assembly level wi th the adsp-2126x, adsp-21160, and adsp-21161, and with the first generation adsp-2106x sharc processors. the adsp-21367/adsp-21368/ adsp-21369 share architectural fe atures with the adsp-2126x and adsp-2116x simd sharc processors, as detailed in the following sections. simd computational engine the processors contain two comp utational processing elements that operate as a single-instruction, multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing ele- ments, but each processing elem ent operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements. because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycl e. the three units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel table 1. processor benchmarks (at 333 mhz) benchmark algorithm speed (at 333 mhz) 1024 point complex fft (radix 4, with reversal) 27.9 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode. 1.5 ns iir filter (per biquad) 1 6.0 ns matrix multiply (pipelined) [33] [31] [44] [41] 13.5 ns 23.9 ns divide (y/) 10.5 ns inverse square root 16.3 ns
adsp-21367/adsp-21368/adsp-21369 rev. a | page 5 of 56 | august 2006 alu and multiplier operations occur in both processing ele- ments. these computation unit s support ieee 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each pro- cessing element. the register fi les transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined with the adsp-2136x enhanced har- vard architecture, allow unco nstrained data flow between computation units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. single-cycle fetch of instruction and four operands the adsp-21367/adsp-21368/adsp-21369 feature an enhanced harvard architecture in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data (see figure 1 on page 1 ). with separate program and data memory buses and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. instruction cache the processors include an on -chip instruction cache that enables three-bus operat ion for fetching an instruction and four data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators with zero-overhead hardware circular buffer support the adsp-21367/adsp-21368/adsp -21369 have two data address generators (dags). the dags are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second- ary). the dags automaticall y handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise programming. for example, the adsp-21367/adsp-21368/adsp-2 1369 can conditionally exe- cute a multiply, an add, and a subtract in both processing elements while branching and fetc hing up to four 32-bit values from memoryall in a single instruction. memory architecture the adsp-21367/adsp-21368/ad sp-21369 processors add the following architectural features to the simd sharc family core. on-chip memory the processors contain two mega bits of internal ram and six megabits of internal mask-programmable rom. each block can be configured for different combin ations of code and data stor- age (see table 2 on page 6 ). each memory block supports single-cycle, independent accesses by the core processor and i/o processor. the memory architecture, in combination with its separate on-chip buses, allow tw o data transfers from the core and one from the i/o processor, in a single cycle. the sram can be configured as a maximum of 64k words of 32-bit data, 128k words of 16-bi t data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is per- formed in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data usin g the dm bus for transfers, and the other block stores instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to each memory block, assures si ngle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. external memory the external port provides a hi gh performance, glueless inter- face to a wide variety of industry-standard memory devices. the 32-bit wide bus may be used to interface to synchronous and/or asynchronous memory devices th rough the use of its separate internal memory controllers. the first is an sdram controller for connection of industry-standard synchronous dram devices and dimms (dual inline memory module), while the second is an asynchronous me mory controller intended to interface to a variety of memory devices. four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. nonsdram external memory address space is shown in table 3 . sdram controller the sdram controller provides an interface of up to four sepa- rate banks of industry-standard sdram devices or dimms, at speeds up to f sclk . fully compliant with the sdram standard, each bank has its own me mory select line (ms0 Cms3 ), and can be configured to contain be tween 16m bytes and 128m bytes of memory. sdram external memory address space is shown in table 4 .
rev. a | page 6 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 the controller maintains all of the memory banks as a contigu- ous address space so that the processor sees this as a single address space, even if different size devices are used in the different banks. a set of programmable timing para meters is available to config- ure the sdram banks to support slower memory devices. the memory banks can be configured as either 32 bits wide for max- imum performance and bandwidth or 16 bits wide for minimum device count an d lower system cost. the sdram controller address, data, clock, and control pins can drive loads up to 30 pf. fo r larger memory systems, the sdram controller external buffer timing should be selected and external buffering should be provided so that the load on the sdram controller pins does not exceed 30 pf. asynchronous controller the asynchronous memory controller provides a configurable interface for up to four sepa rate banks of memory or i/o devices. each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including sram, rom, flash, and eprom, as well as i/o devices that interface with standard memory con- trol lines. bank 0 occupies a 14m word window and banks 1, 2, and 3 occupy a 16m word window in the processors address space but, if not fully populated, these windows are not made contiguous by the memory contro ller logic. the banks can also be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of interfacing to a range of memories and i/o devices tailored either to high performance or to low cost and power. table 2. internal memory space 1 iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom (reserved) 0x0004 0000C0x0004 bfff block 0 rom (reserved) 0x0008 0000C0x0008 ffff block 0 rom (reserved) 0x0008 0000C0x0009 7fff block 0 rom (reserved) 0x0010 0000C0x0012 ffff reserved 0x0004 f000C0x0004 ffff reserved 0x0009 4000C0x0009 ffff reserved 0x0009 e000C0x0009 ffff reserved 0x0013 c000C0x0013 ffff block 0 sram 0x0004 c000C0x0004 efff block 0 sram 0x0009 0000C0x0009 3fff block 0 sram 0x0009 8000C0x0009 dfff block 0 sram 0x0013 0000C0x0013 bfff block 1 rom (reserved) 0x0005 0000C0x0005 bfff block 1 rom (reserved) 0x000a 0000C0x000a ffff block 1 rom (reserved) 0x000a 0000C0x000b 7fff block 1 rom (reserved) 0x0014 0000C0x0016 ffff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b ffff reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 1 sram 0x0005 c000C0x0005 efff block 1 sram 0x000b 0000C0x000b 3fff block 1 sram 0x000b 8000C0x000b dfff block 1 sram 0x0017 0000C0x0017 bfff block 2 sram 0x0006 0000C0x0006 0fff block 2 sram 0x000c 0000C0x000c 1554 block 2 sram 0x000c 0000C0x000c 1fff block 2 sram 0x0018 0000C0x0018 3fff reserved 0x0006 1000C 0x0006 ffff reserved 0x000c 1555C0x000c 3fff reserved 0x000c 2000C0x000d ffff reserved 0x0018 4000C0x001b ffff block 3 sram 0x0007 0000C0x0007 0fff block 3 sram 0x000e 0000C0x000e 1554 block 3 sram 0x000e 0000C0x000e 1fff block 3 sram 0x001c 0000C0x001c 3fff reserved 0x0007 1000C0x0007 ffff reserved 0x000e 1555C0x000f ffff reserved 0x000e 2000C0x000f ffff reserved 0x001c 4000C0x001f ffff 1 the adsp-21368 and adsp-21369 processors include a customer-def inable rom block. please contact your analog devices sales repre sentative for additional details. table 3. external memory for nonsdram addresses bank size in words address range bank 0 14m 0x0020 0000 C 0x00ff ffff bank 1 16m 0x0400 0000 C 0x04ff ffff bank 2 16m 0x0800 0000 C 0x08ff ffff bank 3 16m 0x0c00 0000 C 0x0cff ffff table 4. external memory for sdram addresses bank size in words address range bank 0 62m 0x0020 0000 C 0x03ff ffff bank 1 64m 0x0400 0000 C 0x07ff ffff bank 2 64m 0x0800 0000 C 0x0bff ffff bank 3 64m 0x0c00 0000 C 0x0fff ffff
adsp-21367/adsp-21368/adsp-21369 rev. a | page 7 of 56 | august 2006 the asynchronous memory controller is capable of a maximum throughput of 264m by tes/s using a 66 mhz external bus speed. other features include 8-bit to 32-bit and 16-bit to 32-bit pack- ing and unpacking, booting from bank select 1, and support for delay line dma. shared external memory the adsp-21368 processor support s connecting to common shared external memo ry with other adsp-21368 processors to create shared external bus pr ocessor systems. this support includes: ? distributed, on-chip arbitratio n for the shared external bus ? fixed and rotating priority bus arbitration ? bus time-out logic ? bus lock multiple processors can share th e external bus with no addi- tional arbitration logic. arbitrat ion logic is included on-chip to allow the connection of up to four processors. bus arbitration is accomp lished through the br1-4 signals and the priority scheme for bus arbitration is determined by the set- ting of the rpba pin. table 5 on page 12 provides descriptions of the pins used in multiprocessor systems. input/output features the i/o processor provides 34 channels of dma, as well as an extensive set of peripherals. these include a 20-pin digital audio interface which controls: ? eight serial ports ? s/pdif receiver/transmitter ? four precision clock generators ? four stereo sample rate converters ? internal data port/parallel data acquisition port the processors also contain a 14- pin digital periph eral interface which controls: ? three general-purpose timers ? two serial peripheral interfaces ?two universal asynchrono us receiver/transmitters (uarts) ? a two-wire interface (i 2 c-compatible) dma controller the processors on-chip dma cont roller allows data transfers without processor intervention . the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while th e core is simultaneously exe- cuting its program instructio ns. dma transfers can occur between the processors internal me mory and its serial ports, the spi-compatible (serial peripher al interface) ports, the idp (input data port), the parallel da ta acquisition port (pdap), or the uart. thirty-four channels of dma are available on the adsp-21367/adsp-21368/adsp -2136916 via the serial ports, eight via the input data port, four for the uarts, two for the spi interface, two for th e external port, and two for memory-to-memory transfers. programs can be downloaded to the processors using dma tran sfers. other dma features include interrupt generation upon completion of dma trans- fers, and dma chaining for automatic linked dma transfers. delay line dma the adsp-21367/adsp-21368/adsp-21369 processors pro- vide delay line dma functionalit y. this allows processor reads and writes to external delay line buffers (in external memory, sram, or sdram) with limited core interaction. digital audio and digital peripheral interfaces (dai/dpi) the digital audio and digital periphal interfaces (dai and dpi) provide the ability to connect va rious peripherals to any of the dsps dai or dpi pins (dai_p20C1 and dpi_p14C1). programs make these connections using the signal routing units (sru1 and sru2), shown in figure 1 . the srus are matrix routing units (or group of multiplexers) that enable the peripherals provided by the dai and dpi to be interconnected under software cont rol. this allows easy use of the associated peripherals for a much wider variety of applica- tions by using a larger set of al gorithms than is possible with nonconfigurable signal paths. the dai and dpi also include ei ght serial ports, an s/pdif receiver/transmitter, four prec ision clock generators (pcg), eight channels of synchronous sample rate converters, and an input data port (idp). the idp provides an additional input path to the processor core, config urable as either eight channels of i 2 s serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquis ition port. each data channel has its own dma channel that is independent from the proces- sors serial ports. for complete information on using the dai and dpi, see the adsp-21368 sharc proces sor hardware reference . serial ports the processors feature eight sync hronous serial ports (sports) that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devi ces such as analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight sports are enabled, or eight full duplex tdm streams of 128 channels per frame. the serial ports operate at a maximum data rate of 50m bits/s. serial port data can be automatically transferred to and from on-chip memory via dedicated dma channels. each of the serial ports can work in conjunct ion with another serial port to provide tdm support. one sport provides two transmit sig- nals while the other sport provides the two receive signals. the frame sync and clock are shared.
rev. a | page 8 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 serial ports operate in five modes: ? standard dsp serial mode ?multichannel (tdm ) mode with support for packed i 2 s mode ?i 2 s mode ?packed i 2 s mode ? left-justified sample pair mode left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitte d/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. programs have control over var- ious attributes of this mode. each of the serial ports supports the left-justified sample pair and i 2 s protocols (i 2 s is an industry-standard interface com- monly used by audio codecs, adcs, and dacs such as the analog devices ad183x family), with two data pins, allowing four left-justified sample pair or i 2 s channels (using two stereo devices) per serial port, with a maximum of up to 32 i 2 s chan- nels. the serial ports permit little-endian or big-endian transmission formats an d word lengths selectab le from 3 bits to 32 bits. for the left-justified sample pair and i 2 s modes, data- word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchron ization and transmit modes as well as optional -law or a-law companding selection on a per channel basis. serial port clocks and frame syncs can be inter- nally or extern ally generated. the serial ports also contain fr ame sync error detection logic where the serial ports detect fram e syncs that arrive early (for example, frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). all the serial ports also share one dedicated error interrupt. s/pdif-compatible digital audio receiver/transmitter and synchronous/asynchronous sample rate converter the s/pdif receiver/transmitter has no separate dma chan- nels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the receiver/transmitter can be formatted as left-justified, i 2 s, or right-justified with word widt hs of 16, 18, 20, or 24 bits. the serial data, clock, and frame sync inputs to the s/pdif receiver/transmitter are routed th rough the signal routing unit (sru). they can come from a va riety of sources such as the sports, external pins, the precision clock generators (pcgs), or the sample rate converters (src) and are controlled by the sru control registers. the sample rate converter (src) contains four src blocks and is the same core as that us ed in the ad1896 192 khz stereo asynchronous sample rate conver ter and provides up to 128 db snr. the src block is used to perform synchronous or asyn- chronous sample rate conversi on across indepe ndent stereo channels, without using internal processor resources. the four src blocks can also be configur ed to operate to gether to con- vert multichannel audio data without phase mismatches. finally, the src can be used to clean up audio data from jittery clock sources such as the s/pdif receiver. digital peripheral interface (dpi) the digital peripheral interfac e provides connections to two serial peripheral interface port s (spi), two universal asynchro- nous receiver-transmitters (u arts), a two-wire interface (twi), 12 flags, and three general-purpose timers. serial peripheral (compatible) interface the processors contain two serial peripheral interface ports (spis). the spi is an industry-s tandard synchronous serial link, enabling the spi-compatible port to communicate with other spi-compatible devices. the spi consists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchro- nous serial interface, supportin g both master and slave modes. the spi port can operate in a multimaster environment by interfacing with up to four othe r spi-compatible devices, either acting as a master or slave device. the adsp-21367/ adsp-21368/adsp-21369 spi-compat ible peripheral imple- mentation also features programmable baud rate and clock phase and polarities. the spi-comp atible port uses open drain drivers to support a multimaste r configuration and to avoid data contention. uart port the processors provide a full-du plex universal asynchronous receiver/transmitter (uart) port , which is fully compatible with pc-standard uarts. the ua rt port provides a simpli- fied uart interface to other peripherals or hosts, supporting full-duplex, dma-support ed, asynchronous transfers of serial data. the uart also has mult iprocessor commun ication capa- bility using 9-bit address detection. this allows it to be used in multidrop networks through th e rs-485 data interface stan- dard. the uart port also includes support for five data bits to eight data bits, one stop bit or two stop bits, and none, even, or odd parity. the uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. the uart ports baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk / 1,048,576) to (f sclk /16) bits per second. ? supporting data formats from 7 bits to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. where the 16-bit uart_divisor comes from the dlh register (most significant eight bits) and dll register (least significant eight bits).
adsp-21367/adsp-21368/adsp-21369 rev. a | page 9 of 56 | august 2006 in conjunction with the general-purpose timer functions, auto- baud detection is supported. timers the adsp-21367/adsp-21368/adsp -21369 have a total of four timers: a core timer that can generate periodic software interrupts and three general-purp ose timers that can generate periodic interrupts and be inde pendently set to operate in one of three modes: ? pulse waveform generation mode ? pulse width count/capture mode ? external event watchdog mode the core timer can be configur ed to use flag3 as a timer expired signal, and each genera l purpose timer has one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32- bit pulse width register. a sin- gle control and status register enables or disables all three general-purpose timers independently. two-wire interface port (twi) the twi is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the i 2 c bus protocol. the twi master incorporates the following features: ? simultaneous master and sl ave operation on multiple device systems with suppo rt for multimaster data arbitration ? digital filtering and timed event processing ? 7-bit and 10-bit addressing ? 100k bits/s and 400k bits/s data rates ? low interrupt rate pulse-width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programmed to generate the required switching patterns for various a pplications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-align ed pwm wave- forms. in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four pwm waveforms). the entire pwm module has four groups of four pwm outputs each. therefore, this module generates 16 pwm outputs in total. each pwm group produces two pairs of pwm signals on the four pwm outputs. the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single update mode or double update mode. in single update mode the duty cycle values are programmab le only once per pwm period. this results in pwm patterns that are symmetrical about the midpoint of the pwm period. in double update mode, a second updating of the pwm regist ers is implemented at the midpoint of the pwm period. in this mode, it is possible to pro- duce asymmetrical pwm patterns that produce lower harmonic distortion in three- phase pwm inverters. rom-based security the adsp-21367/adsp-21368/adsp -21369 have a rom secu- rity feature that provides hard ware support for securing user software code by preventing unauthorized reading from the internal code when enabled. wh en using this feature, the pro- cessor does not boot-load any external code, executing exclusively from internal sr am/rom. additionally, the pro- cessor is not freely accessible vi a the jtag port. instead, a unique 64-bit key, which must be scanned in through the jtag or test access port will be assign ed to each cust omer. the device will ignore a wrong key. emulation features and external boot modes are only available after the correct key is scanned. system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory of the processors can be booted up at sys- tem power-up from an 8-bit ep rom via the external port, an spi master or slave, or an internal boot. booting is determined by the boot configuration (boot_cfg1C0) pins (see table 7 on page 15 ). selection of the boot so urce is controlled via the spi as either a master or slav e device, or it can immediately begin executing from rom. power supplies the processors have separate power supply connections for the internal (v ddint ), external (v ddext ), and analog (a vdd /a vss ) power supplies. the internal and analog supplies must meet the 1.3 v requirement for the 333 mh z device and 1.2 v for the 266 mhz device. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same power supply. note that the analog supply pin (a vdd ) powers the processors internal clock generator pll. to produce a stable clock, it is rec- ommended that pcb designs use an external filter circuit for the a vdd pin. place the filter components as close as possible to the a vdd /a vss pins. for an example circuit, see figure 2 . (a recom- mended ferrite chip is the murata blm18ag102sn1d). to reduce noise coupling, the pcb should use a parallel pair of power and ground planes for v ddint and gnd. use wide traces to connect the bypass capacitors to the analog power (a vdd ) and ground (a vss ) pins. note that the a vdd and a vss pins specified in figure 2 are inputs to the processo r and not the analog ground plane on the boardthe a vss pin should connect directly to dig- ital ground (gnd) at the chip.
rev. a | page 10 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test a ccess port of the adsp-21367/ adsp-21368/adsp-21369 processo rs to monitor and control the target board processor duri ng emulation. analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, an d processor stacks. the processors jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. development tools the processors are supported wi th a complete set of cross- core ? software and hardware development tools, including analog devices emulators and visualdsp++ ? development environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-21367/adsp- 21368/adsp-21369. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accura te instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the sharc has architectural features that impr ove the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code executio n metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and manage all of the sharc devel- opment tools, including the colo r syntax highlighting in the visualdsp++ editor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-s liced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists th e developer with many error-prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk-based objects, and vi sualizing the system state, when debugging an application that uses the vdk. visualdsp++ component softwa re engineering (vcse) is analog devices technology fo r creating, using, and reusing software components (indepen dent modules of substantial functionality) to quickly and reliably assemble software applications. the user can do wnload components from the web, drop them into the application, and publish component archives from within visualds p++. vcse supports component implementation in c/c++ or assembly language. figure 2. analog power (a vdd ) filter circuit hi-z ferrite bead chip locate all components close to a vdd and a vss pins a vdd a vss 100nf 10nf 1nf adsp-213xx v ddint
adsp-21367/adsp-21368/adsp-21369 rev. a | page 11 of 56 | august 2006 use the expert linker to visua lly manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical fo rm, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. the expert linker is fully compatible with the existing linker def- inition file (ldf), allowing the developer to move between the graphical and textual environments. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc proce ssor pc plug-in cards. third- party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supp lied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in-circuit emulation is assured by the use of the processors jtag inter- facethe emulator does not affe ct target syst em loading or timing. the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and com- mands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. evaluation kit analog devices offers a range of ez-kit lite ? evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board alon g with an evaluation suite of the visualdsp++ development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample application programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-k it lite board connects the board to the usb port of th e users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on -board flash device to store user-specific boot code, enabling the board to run as a stand- alone unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software for the ez-kit lite or any custom-defined system. connecting one of analog devices jtag emulators to the ez-kit li te board enables high speed, non-intrusive emulation. additional information this data sheet provides a general overview of the adsp-21367/adsp-21368/adsp-21369 architecture and func- tionality. for detailed inform ation on the ad sp-2136x family core architecture and inst ruction set, refer to the adsp-21368 sharc processor hardware reference and the adsp- 2136x/adsp-2137x sharc processor programming reference .
rev. a | page 12 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 pin function descriptions the following symbols appear in the type column of table 5 : a = asynchronous, g = ground, i = input, o = output, o/t = output three-state, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, (pd) = pull-down resistor, (pu) = pull-up resistor. table 5. pin list name type state during/ after reset (id = 00x) description addr 23C0 o/t (pu) 1 pulled high/ driven low external address. the processors output addresses for external memory and periph- erals on these pins. data 31C0 i/o (pu) 1 pulled high/ pulled high external data. data pins can be multiplexed to support external memory interface data (i/o), the pdap (i), flags (i/o), and pwm (o). after reset, all data pins are in emif mode and flag(0-3) pins are in flags mode (default). when configured using the idp_pdap_ctl register, idp channel 0 scans the data 31C8 pins for parallel input data. dai _p 20C1 i/o with pro- grammable pu 2 pulled high/ pulled high digital audio interface . these pins provide the physical interface to the dai sru. the dai sru configuration registers define the combination of on-chip audiocentric periph- eral inputs or outputs connected to the pin, and to the pins output enable. the configuration registers then determines the exact behavior of th e pin. any input or output signal present in the dai sru may be routed to any of these pins. the dai sru provides the connection from the serial po rts (8), the src module, the s/pdif module, input data ports (2), and the precision clock generators (4), to the dai_p20C1 pins. pull- ups can be disabled via the dai_pin_pullup register. dpi _p 14C1 i/o with pro- grammable pu 2 pulled high/ pulled high digital peripheral interface. these pins provide the physical interface to the dpi sru. the dpi sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the dpi sru may be routed to any of these pins. the dpi sru provides the connection from the timers (3), spis (2), uarts (2), flags (12) twi (1), and general-purpose i/o (9) to the dpi_p14C1 pins. the twi output is an open-drain outputso the pins used for i 2 c data and clock should be connected to logic level 0. pull-ups can be disabled via the dpi_pin_pullup register. ack i (pu) 1 memory acknowledge. external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. rd o/t (pu) 1 pulled high/ driven high external port read enable. rd is asserted whenever the processors read a word from external memory. wr o/t (pu) 1 pulled high/ driven high external port write enable. wr is asserted when the processors write a word to external memory. sdras o/t (pu) 1 pulled high/ driven high sdram row address strobe. connect to sdrams ras pin. in conjunction with other sdram command pins, defines the operation for the sdram to perform. sdcas o/t (pu) 1 pulled high/ driven high sdram column address select. connect to sdrams cas pin. in conjunction with other sdram command pins, defines the operation for the sdram to perform. sdwe o/t (pu) 1 pulled high/ driven high sdram write enable. connect to sdrams we or w buffer pin.
adsp-21367/adsp-21368/adsp-21369 rev. a | page 13 of 56 | august 2006 sdcke o/t (pu) 1 pulled high/ driven high sdram clock enable. connect to sdrams cke pin. enables and disables the clk signal. for details, see the data sheet supplied with the sdram device. sda10 o/t (pu) 1 pulled high/ driven low sdram a10 pin. enables applications to refresh an sdram in parallel with non- sdram accesses. this pin replaces the ds ps a10 pin only during sdram accesses. sdclk0 o/t high-z/driving sdram clock output 0. sdclk1 o/t sdram clock output 1. ad d i t i o n a l c lo c k fo r s d r a m d e v i c e s. fo r s ys tem s w i t h m u l t i p l e sdram devices, handles the increased clock load requirements, eliminating need of off-chip clock buffers. either sdclk1 or both sdclkx pins can be three-stated. ms 0C1 o/t (pu) 1 pulled high/ driven high memory select lines 0C1. these lines are asserted (low) as chip selects for the corre- sponding banks of external memory. the ms 3-0 lines are decoded memory address lines that change at the same time as the othe r address lines. when no external memory access is occurring, the ms 3-0 lines are inactive; they are active, however, when a condi- tional memory access instruction is executed, whether or not the condition is true. the ms 1 pin can be used in eport/flash boot mode. see the hardware reference for more information. flag[0]/irq0 i/o high-z/high-z flag0/interrupt request 0. flag[1]/irq1 i/o high-z/high-z flag1/interrupt request 1. flag[2]/irq2 / ms 2 i/o with pro- grammable pu (for ms mode) high-z/high-z flag2/interrupt request 2/memory select 2. flag[3]/timexp/ ms 3 i/o with pro- grammable pu (for ms mode) high-z/high-z flag3/timer expired/memory select 3. tdi i (pu) test data input (jtag). provides serial data for the boundary scan logic. tdo o/t test data output (jtag). serial scan output of the boundary scan path. tms i (pu) test mode select (jtag). used to control the test state machine. tck i test clock (jtag). provides a clock for jtag bounda ry scan. tck must be asserted (pulsed low) after power-up, or held lo w for proper operation of the processor trst i (pu) test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the processor. emu o/t (pu) emulation status. must be connected to the adsp-21367/adsp-21368/adsp-21369 analog devices dsp tools product line of jtag emulator target board connectors only. clk_cfg 1C0 i core/clkin ratio control. these pins set the start-up clock frequency. see table 8 for a description of the cloc k configuration modes. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. boot_cfg 1C0 i boot configuration select. these pins select the boot mode for the processor. the boot_cfg pins must be valid before reset is asserted. see table 7 for a description of the boot modes. table 5. pin list name type state during/ after reset (id = 00x) description
rev. a | page 14 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 reset i processor reset. resets the processor to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. xtal o crystal oscillator terminal. used in conjunction with clkin to drive an external crystal. clkin i local clock in. used with xtal. clkin is the proce ssors clock input. it configures the processors to use either its internal clock generator or an external clock source. con- necting the necessary compon ents to clkin and xtal en ables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the processor to use an external clock such as an external clock oscillator. clkin may not be halted, changed, or operated below the specified frequency. resetout/ clkout o/t driven low/ driven high reset out/local clock out. reset out provide a 4096 cycle delay that allows the pll to lock. this pin can also be configured as a clkout signal to clock synchronous periph- erals and memory. the functionality can be switched between the pll output clock and reset out by setting bit 12 of the pm ctl register. the default is reset out. br 4C1 i/o (pu) 1 pulled high/ pulled high external bus request. used by the adsp-21368 processor to arbitrate for bus master- ship. a processor only drives its own br x line (corresponding to the value of its id2-0 inputs) and monitors all others. in a system with less than four processors, the unused br x pins should be tied hi gh; the processors own br x line must not be tied high or low because it is an output. id 2C0 i (pd) processor id. determines which bus request (br 4C1 ) is used by the adsp-21368 pro- cessor. id = 001 corresponds to br 1, id = 010 corresponds to br 2 , and so on. use id = 000 or 001 in single-processor system s. these lines are a system configuration selection that should be hardwired or only changed at reset. id = 101,110, and 111 are reserved. rpba i (pu) 1 rotating priority bus arbitration select. when rpba is high, rotating priority for the adsp-21368 external bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configurat ion selection which must be set to the same value on every processor in the system. 1 the pull-up is always enabled on the adsp-21367 and adsp-21369 processors. the pull-up on the adsp-21368 processor is only enab led on the processor with id 2C0 = 00x 2 pull-up can be enabled/disabled, valu e of pull-up cannot be programmed. table 5. pin list name type state during/ after reset (id = 00x) description
adsp-21367/adsp-21368/adsp-21369 rev. a | page 15 of 56 | august 2006 data modes the upper 32 data pins of the external memory interface are muxed (using bits in the sysctl register) to support the exter- nal memory interface data (input/output), the pdap (input only), the flags (input/output), and the pwm channels (out- put). table 6 provides the pin settings. boot modes core instruction rate to clkin ratio modes for details on processor timing, see timing specifications and figure 4 on page 19 . table 6. function of data pins data pin mode data31C16 data15C8 data7C0 000 epdata32C0 001 flags/pwm15C0 1 epdata15C0 010 flags/pwm15C0 1 flags15C8 epdata7C0 011 flags/pwm15C0 1 flags15C0 100 pdap (data + ctrl) epdata7C0 101 pdap (data + ctrl) flags7C0 110 reserved 111 three-state all pins 1 these signals can be flags or pwm or a mix of both. however, they can be selected only in groups of four. their function is det ermined by the control signals flags/pwm_sel. for more information, see the adsp-21368 sharc processor hardware reference . table 7. boot mode selection boot_cfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 eprom/flash boot table 8. core instruction rate/clkin ratio selection clk_cfg1C0 core to clkin ratio 00 6:1 01 32:1 10 16:1
rev. a | page 16 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 specifications operating conditions parameter 1 1 specifications subject to change without notice. description 333 mhz 266 mhz min max min max unit v ddint internal (core) supply voltage 1.235 1.365 1.14 1.26 v a vdd analog (pll) supply voltage 1.235 1.365 1.14 1.26 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v ih 2 2 applies to input and bidirectional pins: datax, ack, rpba, brx , idx, flagx, dai_px, dpi_px, boot_cfgx, clk_cfgx, reset , tck, tms, tdi, trst . high level input voltage @ v ddext = max 2.0 v ddext + 0.5 2.0 v ddext + 0.5 v v il 2 low level input voltage @ v ddext = min C0.5 +0.8 C0.5 +0.8 v v ih _ clkin 3 3 applies to input pin clkin. high level input voltage @ v ddext = max 1.74 v ddext + 0.5 1.74 v ddext + 0.5 v v il _ clkin 3 low level input voltage @ v ddext = min C0.5 +1.19 C0.5 +1.19 v t j junction temperature 208-lead mqfp @ t ambient 0 c to +70 c 256-ball sbga @ t ambient 0 c to +70 c 256-ball sbga @ t ambient C40 c to +85 c 0 C40 +110 +125 0+120 c c c
adsp-21367/adsp-21368/adsp-21369 rev. a | page 17 of 56 | august 2006 electrical characteristics parameter 1 description test conditions min typ max unit v oh 2 high level output voltage @ v ddext = min, i oh = C1.0 ma 3 2.4 v v ol 2 low level output voltage @ v ddext = min, i ol = 1.0 ma 3 0.4 v i ih 4, 5 high level input current @ v ddext = max, v in = v ddext max 10 a i il 4, 6, 7 low level input current @ v ddext = max, v in = 0 v 10 a i ihpd 6 high level input current pull-down @ v ddext = max, v in = 0 v 250 a i ilpu 5 low level input current pull-up @ v ddext = max, v in = 0 v 200 a i ozh 8, 9 three-state leakage current @ v ddext = max, v in = v ddext max 10 a i ozl 8, 10 three-state leakage current @ v ddext = max, v in = 0 v 10 a i ozlpu 9 three-state leakage current pull-up @ v ddext = max, v in = 0 v 200 a i dd - intyp 11 supply current (internal) t cclk = 3.75 ns, v ddint = 1.2 v, 25c t cclk = 3.00 ns, v ddint = 1.3 v, 25c 700 900 ma ma ai dd 12 supply current (analog) a vdd = max 10 ma c in 13, 14 input capacitance f in = 1 mhz, t case = 25c, v in = 1.3 v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidirect ional pins: addrx, datax, rd , wr , msx , brx , flagx, dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10, sdclkx, emu , tdo, clkout. 3 see output drive currents on page 47 for typical drive current capabilities. 4 applies to input pins without internal pull- ups: boot_cfgx, clk_cfgx, clkin, reset , tck. 5 applies to input pins with internal pull-ups: ack, rpba, tms, tdi, trst . 6 applies to input pins with internal pull-downs: idx. 7 applies to input pins with interna l pull-ups disabled: ack, rpba. 8 applies to three-statable pins withou t internal pull-ups: flagx, sdclkx, tdo. 9 applies to three-statable pins with internal pull-ups: addrx, datax, rd , wr , msx , brx , dai_px, dpi_px, sdras , sdcas, sdwe , sdcke, sda10, emu . 10 applies to three-statable pins with inte rnal pull-ups disabled: addrx, datax, rd , wr , msx , brx , dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10 11 see engineer-to-engineer note 299 for further information. 12 characterized, but not tested. 13 applies to all signal pins. 14 guaranteed, but not tested.
rev. a | page 18 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 package information the information presented in figure 3 provides details about the package branding fo r the adsp-21367/adsp-21368/ adsp-21369 processors. for a comp lete listing of product avail- ability, see ordering guide on page 56 . maximum power dissipation see engineer-to-engineer note (ee-299) for detailed thermal and power information regarding maximum power dissipation. for information on package thermal specifications, see thermal characteristics on page 48 . absolute maximum ratings stresses greater than those listed in table 10 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity figure 3. typical package brand table 9. package brand information brand key field description t temperature range pp package type z lead free option (optional) cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code vvvvvv.x n.n tppz-cc s adsp-2136x a yyww country_of_origin table 10. absolute maximum ratings parameter rating internal (core) supply voltage (v ddint )C0.3 v to +1.5 v analog (pll) supply voltage (a vdd )C0.3 v to +1.5 v external (i/o) supply voltage (v ddext )C0.3 v to +4.6 v input voltage C0.5 v to +3.8 v output voltage swing C0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range C65 c to +150 c junction temperature under bias 125 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipmen t and can discharge without detection. although the adsp-21367/adsp-21368/adsp-21369 feature propr ietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid perf ormance degradation or loss of functionality.
adsp-21367/adsp-21368/adsp-21369 rev. a | page 19 of 56 | august 2006 timing specifications the processors internal clock (a multiple of clkin) provides the clock signal for timing inte rnal memory, processor core, and serial ports. during reset, prog ram the ratio between the proces- sors internal clock frequenc y and external (clkin) clock frequency with the clk_cfg1C0 pins (see table 8 on page 15 ). to determine switching frequencie s for the serial ports, divide down the internal clock, usin g the programmable divider con- trol of each port (divx for the serial ports). the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an internal phase-locked loop (pll). this pll-based clocking minimi zes the skew between the sys- tem clock (clkin) signal and th e processors internal clock. figure 4 shows core to clkin ratios of 6:1, 16:1, and 32:1 with external oscillator or crystal. no te that more ratios are possible and can be set through software using the power management control register (pmctl). for more information, see the adsp-2136x/adsp-2137x sharc processor programming reference . note the definitions of vari ous clock periods shown in table 12 which are a function of clkin and the appropriate ratio con- trol shown in table 11 . table 11. adsp-21367/ad sp-21368/adsp-21369 clkout and cclk clock generation operation timing requirements description calculation clkin input clock 1/t ck cclk core clock 1/t cclk table 12. clock periods timing requirements description 1 t ck clkin clock period t cclk (processor) core clock period t pclk (peripheral) clock period = 2 t cclk t sclk serial port clock period = (t pclk ) sr t sdclk sdram clock period = (t cclk ) sdr t spiclk spi clock period = (t pclk ) spir 1 where: sr = serial port-to-core clock ratio (wide range, determined by sport clkdiv bits in divx register) spir = spi-to-core clock ratio (wide ra nge, determined by spibaud register setting) spiclk = spi clock sdr = sdram-to-core clock ratio (val ues determined by bits 20C18 of the pmctl register) figure 4. core clock and system clock relationship to clkin pllm clkin cclk (core clock) plliclk xtal xtal osc clkout or rstout clk_cfg [1:0] (6:1, 16:1, 32:1) pclk (peripheral clock) indiv 1, 2 diven 2,4,8,16 delay sdclk (sdram clock) 2 2,2.5, 3, 3.5, 4 reset
rev. a | page 20 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 use the exact timing informatio n given. do not attempt to derive parameters from the addi tion or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 39 on page 47 under test conditions for voltage refer- ence levels. switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices.
adsp-21367/adsp-21368/adsp-21369 rev. a | page 21 of 56 | august 2006 power-up sequencing the timing requirements for pr ocessor startup are given in table 13 . table 13. power-up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 +200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 s switching characteristic t corerst core reset deasserted after reset deasserted 4096t ck + 2 t cclk 3, 4 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.2 volt ra ils and 3.3 volt rails. voltage ramp rates can vary from micros econds to hundreds of milliseconds depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. refer to your crystal oscillator manufacturers data sheet for start-up time. assume a 25 ms maximum oscillator start-up time if using the xtal pin and internal oscillator circuit in conjunction with an external crystal. 3 applies after the power-up sequence is co mplete. subsequent resets require reset to be held low a minimum of four clkin cycles in order to properly in itialize and propagate default states at all i/o pins. 4 the 4096 cycle count depends on t srst specification in table 15 . if setup time is not met, 1 additional clkin cycle may be added to the core reset ti me, resulting in 4097 cycles maximum. figure 5. power-up sequencing clkin reset t rstvdd rstout v ddext v ddint t pllrst t clkrst t clkvdd t ivddevdd clk_cfg1-0 t corerst
rev. a | page 22 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 clock input clock signals the processors can use an external clock or a crystal. see the clkin pin description in table 5 . programs can configure the processor to use its internal cl ock generator by connecting the necessary components to clkin and xtal. figure 7 shows the component connections used for a crystal operating in funda- mental mode. note that the clock rate is achieved using a 20.81 mhz crystal and a pll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 333 mhz). to achieve the full core clock rate, progra ms need to configure the multi- plier bits in the pmctl register. table 14. clock input parameter 333 mhz unit min max timing requirements t ck clkin period 18 1 1 applies only for clk_cfg1C0 = 00 and defa ult values for pll control bits in pmctl. 100 2 2 applies only for clk_cfg1C0 = 10 and defa ult values for pll control bits in pmctl. ns t ckl clkin width low 8 1 45 2 ns t ckh clkin width high 8 1 45 2 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 ns t cclk 3 3 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 3.0 1 10 ns t ckj 4, 5 4 actual input jitter should be combined with ac specifications for acc urate timing analysis. 5 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 ps figure 6. clock input clkin t ck t ckh t ckl figure 7. 333 mhz operation (fundamental mode crystal) c1 22pf y1 r1 1m (typical) xtal clkin c2 22pf 24.576mhz r2 47 (typical) adsp-2136x r2 should be chosen to limit crystal drive power. refer to crystal manufacturer?s specifications
adsp-21367/adsp-21368/adsp-21369 rev. a | page 23 of 56 | august 2006 reset interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts. table 15. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequen ce is complete. at power-up, th e processors internal ph ase-locked loop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including startup time of external clock oscillator). figure 8. reset clkin reset t wrst t srst table 16. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk +2 ns figure 9. interrupts dai_p20 - 1 dpi_14 - 1 flag2 - 0 (irq2 - 0) t ipw
rev. a | page 24 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 core timer the following timing specification applies to flag3 when it is configured as the core timer (ctimer). timer pwm_out cycle timing the following timing specification applies to timer0, timer1, and timer2 in pwm_out (pulse-width modulation) mode. timer signals are routed to the dpi_p14C1 pins through the dpi sru. therefore, the timing specifications provided below are valid at the dpi_p14C1 pins. table 17. core timer parameter min max unit switching characteristic t wctim ctimer pulse width 4 t pclk C 1 ns figure 10. core timer flag3 (ctimer) t wctim table 18. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 2 2 (2 31 C 1) t pclk ns figure 11. timer pwm_out timing dpi_p14 - 1 (timer2 - 0) t pwmo
adsp-21367/adsp-21368/adsp-21369 rev. a | page 25 of 56 | august 2006 timer wdth_cap timing the following timing specification applies to timer0, timer1, and timer2 in wdth_cap (pul se width count and capture) mode. timer signals are routed to the dpi_p14C1 pins through the dpi sru. therefore, the ti ming specification provided below are valid at the dpi_p14C1 pins. pin to pin direct routing (dai and dpi) for direct pin connections only (for example, dai_pb01_i to dai_pb02_o). table 19. timer width capture timing parameter min max unit switching characteristic t pw i timer pulse width 2 t pclk 2 (2 31 C 1) t pclk ns figure 12. timer width capture timing dpi_p14 - 1 (timer2 - 0) t pwi table 20. dai pin to pin routing parameter min max unit timing requirement t dpio delay dai pin input valid to dai output valid 1.5 10 ns figure 13. dai pin to pin direct routing dai_pn dpi_pn t dpio dai_pm dpi_pm
rev. a | page 26 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 C dai_p20). table 21. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgip input clock period 24 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + ((2.5 + d) t pcgip ) 10 + ((2.5 + d) t pcgip )ns t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip )ns t pcgow 1 output clock period 2 t pcgip C 1 ns d = fsxdiv, ph = fsxphase. for more information, see the adsp-2136x sharc processor hardware reference for the adsp-21368 processor , precision clock generators chapter. 1 in normal mode. figure 14. precision clock generator (direct pin routing) dai_pn dpi_pn pcg_trigx_i t strig dai_pm dpi_pm pcg_extx_i (clkin) dai_py dpi_py pcg_clkx_o dai_pz dpi_pz pcg_fsx_o t htrig t dpcgio t dtrigfs t pcgip t pcgow t dtrigclk t dpcgio
adsp-21367/adsp-21368/adsp-21369 rev. a | page 27 of 56 | august 2006 flags the timing specifications provided below apply to the flag3C0 and dpi_p14C1 pins, and the serial peripheral interface (spi). see table 5 on page 12 for more information on flag use. table 22. flags parameter min max unit timing requirement t fipw flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw flag3C0 out pulse width 2 t pclk C 1.5 ns figure 15. flags dpi_p14 - 1 (flag3 - 0 in ) (data31 - 0) t fipw dpi_p14 - 1 (flag3 - 0 out ) (data31 - 0) t fopw
rev. a | page 28 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 sdram interface timing (133 mhz sdclk) the 133 mhz access speed is for a single processor. when mul- tiple adsp-21368 processors are co nnected in a shared memory system, the access speed is 100 mhz. table 23. sdram interface timing 1 parameter min max unit timing requirement s t ssdat data setup before sdclk 0.58 ns t hsdat data hold after sdclk 1.23 ns switching characteristic s t sdclk sdclk period 7.5 ns t sdclkh sdclk width high 3.65 ns t sdclkl sdclk width low 3.65 ns t dcad command, addr, data delay after sdclk 2 4.8 ns t hcad command, addr, data hold after sdclk 2 1.5 ns t dsdat data disable after sdclk 5.3 ns t ensdat data enable after sdclk 1.6 ns 1 for f cclk = 333 mhz (sdclk ratio = 1:2.5). 2 command pins include: sdcas , sdras , sdwe , msx , sda10, sdcke. figure 16. sdram interface timing t hcad t hcad t dsdat t ssdat t dcad t ensdat t hsdat t sdclkl t sdclkh t sdclk sdclk data (in) data(out) cmnd addr (out) t dcad
adsp-21367/adsp-21368/adsp-21369 rev. a | page 29 of 56 | august 2006 sdram interface enable/disable timing (133 mhz sdclk) table 24. sdram interface enable/disable timing 1 1 for f cclk = 333 mhz (sdclk ratio = 1:2.5). parameter min max unit switching characteristics t dsdc command disable after clkin rise 2 t pclk + 1 ns t ensdc command enable after clkin rise 4.0 ns t dsdcc sdclk disable after clkin rise 8.5 ns t ensdcc sdclk enable after clkin rise 3.8 ns t dsdca address disable after clkin rise 9.2 ns t ensdca address enable after clkin rise 2 t pclk C 4 4 t pclk ns figure 17. sdram interface enable/disable timing clkin command sdclk addr t dsdc t dsdcc t dsdca t ensdc t ensdca command sdclk addr t ensdcc
rev. a | page 30 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 memory readbus master use these specifications for asyn chronous interfacing to memo- ries. these specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and strobe timing parameters only apply to asynchronous access mode. table 25. memory readbus master parameter min max unit timing requirements t dad address, selects delay to data valid 1, 2 w+t sdclk C5.12 ns t drld rd low to data valid 1 wC 2.9 ns t sds data setup to rd high 2.2 ns t hdrh data hold from rd high 3, 4 0ns t daak ack delay from address, selects 2, 5 t sdclk C9.5+ w ns t dsak ack delay from rd low 4 w C 7.0 ns switching characteristics t drha address selects hold after rd high rh + 0.38 ns t darl address selects to rd low 2 t sdclk C3.3 ns t rw rd pulse width w C 1.2 ns t rwr rd high to wr , rd low hi +t sdclk C 0.8 ns w = (number of wait states specified in amictlx register) t sdclk . hi =rhc + ic (rhc = number of read hold cycles specified in amictlx register) t sdclk ic = (number of idle cycles sp ecified in amictlx register) t sdclk . h = (number of hold cycles specified in amictlx register) t sdclk . 1 data delay/setup: system must meet t dad , t drld , or t sds. 2 the falling edge of ms x is referenced. 3 note that timing for ack, data, rd , wr , and strobe timing parameters only apply to asynchronous access mode. 4 data hold: user must meet t hda or t hdrh in asynchronous access mode. see test conditions on page 47 for the calculation of hold time s given capacitive and dc loads. 5 ack delay/setup: user must meet t daak , or t dsak , for deassertion of ack (low). for asynchron ous assertion of ack (high) user must meet t daak or t dsak . figure 18. memory readbus master ack data t darl t rw t dad t daak t hdrh t rwr t drld t drha t dsak t sds address msx rd wr
adsp-21367/adsp-21368/adsp-21369 rev. a | page 31 of 56 | august 2006 memory writebus master use these specifications for asyn chronous interfacing to memo- ries. these specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and strobe timing parameters on ly apply to asynchronous access mode. table 26. memory writebus master parameter min max unit timing requirements t daak ack delay from address, selects 1, 2 t sdclk C 9.7 + w ns t dsak ack delay from wr low 1, 3 w C 4.9 ns switching characteristics t dawh address, selects to wr deasserted 2 t sdclk C3.1+ w ns t dawl address, selects to wr low 2 t sdclk C2.7 ns t ww wr pulse width w C 1.3 ns t ddwh data setup before wr high t sdclk C3.0+ w ns t dwha address hold after wr deasserted h + 0.15 ns t dwhd data hold after wr deasserted h + 0.02 ns t wwr wr high to wr , rd low t sdclk C1.5+ h ns t ddwr data disable before rd low 2t sdclk C 4.11 ns t wde wr low to data enabled t sdclk C 3.5 ns w = (number of wait states specified in amictlx register) t sdclk . h = (number of hold cycles specified in amictlx register) x t sdclk . 1 ack delay/setup: system must meet t daak , or t dsak , for deassertion of ack (low). for asynchron ous assertion of ack (high) user must meet t daak or t dsak . 2 the falling edge of msx is referenced. 3 note that timing for ack, data, rd , wr , and strobe timing parameters only applies to asynchronous access mode. figure 19. memory writebus master ack data t dawl t ww t daak t wwr t wde t ddwr t dwha t dawh t dsak t ddwh t dwhd address msx wr rd
rev. a | page 32 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 asynchronous memory interface (ami) enable/disable use these specifications for passing bus mastership between adsp-21368 processors (brx ). table 27. ami enable/disable parameter min max unit switching characteristics t enamiac address/control enable after clock rise 4 ns t enamid data enable after clock rise t sclk + 4 ns t disamiac address/control disable after clock rise 8.7 ns t disamid data disable after clock rise 0 ns figure 20. ami enable/disable clkin addr, wr , rd , ms1 - 0 , data t disamiac t disamid t enamiac t enamid addr, wr , rd , ms1 - 0 ,data
adsp-21367/adsp-21368/adsp-21369 rev. a | page 33 of 56 | august 2006 shared memory bus request use these specifications for passing bus mastership between adsp-21368 processors (brx ). table 28. multiprocessor bus request parameter min max unit timing requirements t sbri brx , setup before clkin high 9 ns t hbri brx , hold after clkin high 0.5 ns switching characteristics t dbro brx delay after clkin high 9 ns t hbro brx hold after clkin high 1.0 ns figure 21. shared memory bus request t hbri t sbri clkin t dbro t hbro br x (out) br x (in)
rev. a | page 34 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. serial port signals (sclk, fs, data channel a, data channel b) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. table 29. serial portsexternal clock parameter min max unit timing requirements t sfse 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 2.5 ns t hfse 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 2.5 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width 10 ns t sclk sclk period 20 ns switching characteristics t dfse 2 fs delay after sclk (internally generated fs in either transmit or receive mode) 9.5 ns t hofse 2 fs hold after sclk (internally generated fs in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 9.6 ns t hdte 2 transmit data hold after transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 30. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 7 ns t hfsi 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 fs delay after sclk (internally generated fs in transmit mode) 4 ns t hofsi 2 fs hold after sclk (internally gene rated fs in transmit mode) C1.0 ns t dfsir 2 fs delay after sclk (internally generated fs in receive mode) 9 ns t hofsir 2 fs hold after sclk (internally generated fs in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3 ns t hdti 2 transmit data hold after sclk C1.0 ns t sclkiw 3 transmit or receive sclk width 2 t pclk C 1.5 2 t pclk ns 1 referenced to the sample edge. 2 referenced to drive edge. 3 minimum sport divisor register value.
adsp-21367/adsp-21368/adsp-21369 rev. a | page 35 of 56 | august 2006 table 31. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 10 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. table 32. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 7.75 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justifi ed sample pair as well as dsp serial mode, and mce = 1, mfd = 0. figure 22. external late frame sync 1 1 this figure reflects change s made to support left-jus tified sample pair mode. drive sample drive dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit dai_p20 - 1 (sclk) dai_p20 - 1 (fs) 1st bit 2nd bit t hfse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i dai_p20 - 1 (data channel a/b) note: serial port signals (sclk, fs, data channel a/b ) are routed to the dai_p20 - 1pins using the sru. the timing specifications provided here are valid at the dai_p20 - 1pins. t hfse/i
rev. a | page 36 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 figure 23. serial ports dai_p20 - 1 (sclk) dai_p20 - 1 (fs) drive edge sample edge data receive?internal clock data receive?external clock drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsir t hofsir t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dai_p20 - 1 (data channel a/b) t ddti drive edge sample edge data transmit?internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw t hdti note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t ddte drive edge sample edge data transmit?external clock t sfse t hfse t dfse t hofse t sclkw t hdte dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) drive edge dai_p20 - 1 sclk (int) drive edge drive edge sclk dai_p20 - 1 sclk (ext) t ddtte t ddten t ddtin dai_p20 - 1 (data channel a/b) dai_p20 - 1 (data channel a/b)
adsp-21367/adsp-21368/adsp-21369 rev. a | page 37 of 56 | august 2006 input data port the timing requirements for the idp are given in table 33 . idp signals (sclk, fs, sdata) are routed to the dai_p20C1 pins using the sru. therefore, the ti ming specifications provided below are valid at the dai_p20C1 pins. table 33. idp parameter min max unit timing requirements t sisfs 1 fs setup before sclk rising edge 3.8 ns t sihfs 1 fs hold after sclk rising edge 2.5 ns t sisd 1 sdata setup before sclk rising edge 2.5 ns t sihd 1 sdata hold after sclk rising edge 2.5 ns t idpclkw clock width 9 ns t idpclk clock period 24 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 24. idp master timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) sample edge t sisfs t sihfs t idpclk dai_p20 - 1 (sdata) t idpclkw t sisd t sihd
rev. a | page 38 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 34 . pdap is the parallel mode operation of channel 0 of the idp. for details on the oper ation of the idp, see the idp chapter of the adsp-21368 sharc processor hardware reference . note that the most significant 16 bits of external pdap data can be provided through the data31C16 pins. the remaining four bits can only be sourced through dai_p4C1. the timing below is vali d at the data31C16 pins. table 34. parallel data acquisition port (pdap) parameter min max unit timing requirements t spclken 1 pdap_clken setup before pdap_clk sample edge 2.5 ns t hpclken 1 pdap_clken hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before sclk pdap_clk sample edge 3.85 ns t pdhd 1 pdap_dat hold after sclk pdap_clk sample edge 2.5 ns t pdclkw clock width 7.0 ns t pdclk clock period 24 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk + 3 ns t pdstrb pdap strobe pulse width 2 t pclk C 1 ns 1 source pins of data are addr7C0, data7C0, or dai pins. source pins for sclk and fs are: 1) dai pins, 2) clkin through pcg, or 3) dai pins through pcg. figure 25. pdap timing dai_p20 - 1 (pdap_clk) sample edge t pdsd t pdhd t spclken t hpclken t pdclkw data dai_p20 - 1 (pdap_clken) t pdstrb t pdhldd dai_p20 - 1 (pdap_strobe) t pdclk
adsp-21367/adsp-21368/adsp-21369 rev. a | page 39 of 56 | august 2006 pulse-width modulation generators sample rate converterserial input port the src input signals (sclk, fs , and sdata) are routed from the dai_p20C1 pins using the sru. therefore, the timing spec- ifications provided in table 36 are valid at the dai_p20C1 pins. table 35. pwm timing parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk C 1.5 ns figure 26. pwm timing pwm outputs t pwmw t pwmp table 36. src, serial input port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 4 ns t srchfs 1 fs hold after sclk rising edge 5.5 ns t srcsd 1 sdata setup before sclk rising edge 4 ns t srchd 1 sdata hold after sclk rising edge 5.5 ns t srcclkw clock width 9 ns t srcclk clock period 24 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 27. src serial input port timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) sample edge t srcsfs t srchfs t srcclk dai_p20 - 1 (sdata) t srcclkw t srcsd t srchd
rev. a | page 40 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 sample rate converterserial output port for the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to sclk on the output port. the serial data output, sdata, has a hold time and delay specification with regard to sclk. note that sclk rising edge is the sampling edge and the falling edge is the drive edge. table 37. src, serial output port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 4 ns t srchfs 1 fs hold after sclk rising edge 5.5 ns t srcclkw clock width 9 ns t srcclk clock period 24 ns switching characteristics t srctdd 1 transmit data delay after sclk falling edge 8.9 ns t srctdh 1 transmit data hold after sclk falling edge 1 ns 1 data, sclk, and fs can come from any of the dai pins. sclk and fs can also come via pcg or spor ts. pcgs input can be either c lkin or any of the dai pins. figure 28. src serial output port timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) t srcsfs t srchfs dai_p20 - 1 (sdata) t srctdd t srctdh sample edge t srcclk t srcclkw
adsp-21367/adsp-21368/adsp-21369 rev. a | page 41 of 56 | august 2006 spdif transmitter serial data input to the spdif transmitter can be formatted as left justified, i 2 s, or right justified with word widths of 16, 18, 20, or 24 bits. the following sect ions provide timing for the transmitter. spdif transmitterserial input waveforms figure 29 shows the right-justified mode. lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an lrclk transition, so that when there are 64 sclk periods per lrclk period, the lsb of the data is right- justified to the next lrclk transition. figure 30 shows the default i 2 s-justified mode. lrclk is lo for the left channel and hi for the right channel. data is valid on the rising edge of sclk. the msb is left-justified to an lrclk transition but with a single sclk period delay. figure 31 shows the left-justified mode . lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is left-jus tified to an lrclk transition with no msb delay. figure 29. right-justified mode dai_p20 - 1 lrclk dai_p20 - 1 sclk dai_p20 - 1 sdata left channel right channel msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb lsb msb figure 30. i 2 s-justified mode msb-1 msb-2 lsb+2 lsb+1 lsb left channel right channel msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb dai_p20 - 1 lrclk dai_p20 - 1 sclk dai_p20 - 1 sdata figure 31. left-justified mode left channel right channel msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb+1 msb dai_p20 - 1 lrclk dai_p20 - 1 sclk dai_p20 - 1 sdata
rev. a | page 42 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 spdif transmitter input data timing the timing requirements for the input port are given in table 38 . input signals (sclk, fs, sdata) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifica- tions provided below are valid at the dai_p20C1 pins. oversampling clock (txclk) switching characteristics the spdif transmitter has an ov ersampling clock. this txclk input is divided down to generate the biphase clock. table 38. spdif transmitter input data timing parameter min max unit timing requirements t sisfs 1 fs setup before sclk rising edge 3 ns t sihfs 1 fs hold after sclk rising edge 3 ns t sisd 1 sdata setup before sclk rising edge 3 ns t sihd 1 sdata hold after sclk rising edge 3 ns t sisclkw clock width 36 ns t sisclk clock period 80 ns t sitxclkw transmit clock width 9 ns t sitxclk transmit clock period 20 ns 1 data, sclk, and fs can come from any of the dai pins. sclk and fs can also come via pcg or spor ts. pcgs input can be either c lkin or any of the dai pins. figure 32. spdif transmitter input timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) sample edge t sisd t sisfs t sisclkw dai_p20 - 1 (sdata) dai_p20 - 1 (txclk) t sihd t sihfs t sitxclkw t sitxclk table 39. oversampling clock (txc lk) switching characteristics parameter min max unit txclk frequency for txclk = 768 fs 147.5 mhz txclk frequency for txclk = 512 fs 98.4 mhz txclk frequency for txclk = 384 fs 73.8 mhz txclk frequency for txclk = 256 fs 49.2 mhz frame rate 192.0 khz
adsp-21367/adsp-21368/adsp-21369 rev. a | page 43 of 56 | august 2006 spdif receiver the following section describes timing as it relates to the spdif receiver. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 40. spdif receiver internal digital pll mode timing parameter min max unit switching characteristics t dfsi lrclk delay after sclk 5 ns t hofsi lrclk hold after sclk C2 ns t ddti transmit data delay after sclk 5 ns t hdti transmit data hold after sclk C2 ns t sclkiw 1 transmit sclk width 40 ns 1 sclk frequency is 64 fs where fs = the frequency of lrclk. figure 33. spdif receiver internal digital pll mode timing drive edge sample edge dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) t sclkiw t dfsi t ddti t hofsi t hdti
rev. a | page 44 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 spi interfacemaster the processors contain two spi ports. the primary has dedi- cated pins and the secondary is available through the dpi. the timing provided in table 41 and table 42 on page 45 applies to both. table 41. spi interface protocolmaster switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 8.2 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 tpclk C 2 ns t spichm serial clock high period 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 2.5 ns t hdspidm spiclk edge to data out not valid (data out hold time) 2 ns t sdscim flag3C0in (spi device select) low to first spiclk edge 4 t pclk C 2 ns t hdsm last spiclk edge to flag3C0in high 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1 ns figure 34. spi master timing lsb valid msb valid t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) flag3 - 0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase = 1 t sdscim cphase = 0 t sspidm
adsp-21367/adsp-21368/adsp-21369 rev. a | page 45 of 56 | august 2006 spi interfaceslave table 42. spi interface protocolslave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t pclk 2 t pclk ns ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 6.8 ns t dsdhi spids deassertion to data high impedance 0 6.8 ns t ddspids spiclk edge to data out valid (data out delay time) 9.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk ns figure 35. spi slave timing t hspids t ddspids t dsdhi lsb msb msb valid t dsoe t ddspids t hdspids miso (output) mosi (input) t sspids spids (input) spiclk (cp = 0) (input) spiclk (cp = 1) (input) t sdsco t spichs t spicls t spicls t spiclks t hds t spichs t sspids t hspids t dsdhi lsb valid msb msb valid t dsoe t ddspids miso (output) mosi (input) t sspids lsb valid lsb cphase = 1 cphase = 0 t sdppw t dsov t hdspids
rev. a | page 46 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 jtag test access port and emulation table 43. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys 2 system outputs delay after tck low t ck 2 + 7 ns 1 system inputs = ad15C0, spids , clk_cfg1C0, reset , boot_cfg1C0, miso, mosi, spiclk, dai_px, flag3C0. 2 system outputs = miso, mosi, spiclk, dai_px, ad15C0, rd , wr , flag3C0, clkout, emu . figure 36. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
adsp-21367/adsp-21368/adsp-21369 rev. a | page 47 of 56 | august 2006 output drive currents figure 37 shows typical i-v characteri stics for the output driv- ers of the adsp-21367/adsp-21368/adsp-21369. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 15 on page 23 through table 43 on page 46 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 39 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 39 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 38 ). figure 42 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 40 , figure 41 , and figure 42 may not be linear outside the ranges shown for typical output delay vs. load capacitance and typical output rise time (20% to 80%, v = min) vs. load capacitance. figure 37. typical drive at junction temperature figure 38. equivalent device loading for ac measurements (includes all fixtures) sweep (v ddext ) voltage (v) - 20 03.5 0.5 1.0 1.5 2.0 2.5 3.0 0 - 40 - 30 20 40 - 10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3.11v, 125c 3.3v, 25c 3.47v, -45c v oh 30 10 3.11v, 125c 3.3v, 25c 3.47v, - 45c 1.5v 30pf to output pin 50 + i ol i oh figure 39. voltage reference levels for ac measurements figure 40. typical output rise/fall time (20% to 80%, v ddext = max) figure 41. typical output rise/fall time (20% to 80%, v ddext = min) input or output 1.5v 1.5v load capacitance (pf) 8 0 0 100 250 12 4 2 10 6 r i s e a n d f a l l t i m e s ( n s ) 200 150 50 fall y = 0.0467x + 1.6323 y = 0.045x + 1.524 rise load capacitance (pf) 12 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 rise fall y = 0.049x + 1.5105 y = 0.0482x + 1.4604
rev. a | page 48 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 thermal characteristics the adsp-21367/adsp-21368/adsp -21369 processors are rated for performance over the temperature range specified in operating conditions on page 16 . table 44 and table 45 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies with jesd51-8. test board design complies with jedec stan dard jesd51-9 (sbga) and jesd51-7 (mqfp). the junction -to-case measurement com- plies with mil-std-883. all measurements use a 2s2p jedec test board. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature ( c) t top = case temperature ( c) measured at the top center of the package jt = junction-to-top (of package) characterization parameter is the typical value from table 44 and table 45 . p d = power dissipation (see ee note ee-299) values of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approxi- mation of t j by the equation: where: t a = ambient temperature ( c) values of jc are provided for package comparison and pcb design considerations when an ex ternal heat sink is required. this is only applicable wh en a heat sink is used. values of jb are provided for pack age comparison and pcb design considerations. note that the thermal characteristics val- ues provided in table 44 and table 45 are modeled values. figure 42. typical output delay or hold vs. load capacitance (at junction temperature) load capacitance (pf) 0 200 50 100 150 10 8 o u t p u t d e l a y o r h o l d ( n s ) - 4 6 0 4 2 - 2 y = 0.0488x - 1.5923 t j t top jt p d () + = t j t a ja p d () + = table 44. thermal characteristics for 256-ball sbga parameter condition typical unit ja airflow = 0 m/s 12.5 c/w jma airflow = 1 m/s 10.6 c/w jma airflow = 2 m/s 9.9 c/w jc 0.7 c/w jb 5.3 c/w jt airflow = 0 m/s 0.3 c/w jmt airflow = 1 m/s 0.3 c/w jmt airflow = 2 m/s 0.3 c/w table 45. thermal characte ristics for 208-lead mqfp parameter condition typical unit ja airflow = 0 m/s 25.0 c/w jma airflow = 1 m/s 22.5 c/w jma airflow = 2 m/s 21.6 c/w jc 9.6 c/w jt airflow = 0 m/s 0.7 c/w jmt airflow = 1 m/s 0.8 c/w jmt airflow = 2 m/s 0.9 c/w
adsp-21367/adsp-21368/adsp-21369 rev. a | page 49 of 56 | august 2006 256-ball sbga pinout table 46. 256-ball sbga pin assignme nt (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal a01 nc b01 dai5 c01 dai9 d01 dai10 a02 tdi b02 sdclk1 c02 dai7 d02 dai6 a03 tms b03 trst c03 gnd d03 gnd a04 clk_cfg0 b04 tck c04 v ddext d04 v ddext a05 clk_cfg1 b05 boot_cfg_0 c05 gnd d05 gnd a06 emu b06 boot_cfg_1 c06 gnd d06 v ddext a07 dai4 b07 tdo c07 v ddint d07 v ddint a08 dai1 b08 dai3 c08 gnd d08 gnd a09 dpi14 b09 dai2 c09 gnd d09 v ddext a10 dpi12 b10 dpi13 c10 v ddint d10 v ddint a11 dpi10 b11 dpi11 c11 gnd d11 gnd a12 dpi9 b12 dpi8 c12 gnd d12 v ddext a13 dpi7 b13 dpi5 c13 v ddint d13 v ddint a14 dpi6 b14 dpi4 c14 gnd d14 gnd a15 dpi3 b15 dpi1 c15 gnd d15 v ddext a16 dpi2 b16 reset c16 v ddint d16 gnd a17 clkout b17 data30 c17 v ddint d17 v ddext a18 data31 b18 data29 c18 v ddint d18 gnd a19 nc b19 data28 c19 data27 d19 data26 a20 nc b20 nc c20 nc/rpba 1 d20 data24 e01 dai11 f01 dai14 g01 dai15 h01 dai17 e02 dai8 f02 dai12 g02 dai13 h02 dai16 e03 v ddint f03 gnd g03 gnd h03 v ddint e04 v ddint f04 gnd g04 v ddext h04 v ddint e17 gnd f17 v ddext g17 v ddint h17 v ddext e18 gnd f18 gnd g18 v ddint h18 gnd e19 data25 f19 gnd/id2 1 g19 data22 h19 data19 e20 data23 f20 data21 g20 data20 h20 data18 j01 dai19 k01 flag0 l01 flag2 m01 ack j02 dai18 k02 dai20 l02 flag1 m02 flag3 j03 gnd k03 gnd l03 v ddint m03 gnd j04 gnd k04 v ddext l04 v ddint m04 gnd
rev. a | page 50 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 j17 gnd k17 v ddint l17 v ddint m17 v ddext j18 gnd k18 v ddint l18 v ddint m18 gnd j19 gnd/id1 1 k19 gnd/id0 1 l19 data15 m19 data12 j20 data17 k20 data16 l20 data14 m20 data13 n01 rd p01 sda10 r01 sdwe t01 sdcke n02 sdclk0 p02 wr r02 sdras t02 sdcas n03 gnd p03 v ddint r03 gnd t03 gnd n04 v ddext p04 v ddint r04 gnd t04 v ddext n17 gnd p17 v ddint r17 v ddext t17 gnd n18 gnd p18 v ddint r18 gnd t18 gnd n19 data11 p19 data8 r19 data6 t19 data5 n20 data10 p20 data9 r20 data7 t20 data4 u01 ms0 v01 addr22 w01 gnd y01 gnd u02 ms1 v02 addr23 w02 addr21 y02 nc u03 v ddint v03 v ddint w03 addr19 y03 nc u04 gnd v04 gnd w04 addr20 y04 addr18 u05 v ddext v05 gnd w05 addr17 y05 nc/br1 1 u06 gnd v06 gnd w06 addr16 y06 nc/br2 1 u07 v ddext v07 gnd w07 addr15 y07 xtal2 u08 v ddint v08 v ddint w08 addr14 y08 clkin u09 v ddext v09 gnd w09 a vdd y09 nc u10 gnd v10 gnd w10 a vss y10 nc u11 v ddext v11 gnd w11 addr13 y11 nc/br3 1 u12 v ddint v12 v ddint w12 addr12 y12 nc/br4 1 u13 v ddext v13 v ddext w13 addr10 y13 addr11 u14 v ddext v14 gnd w14 addr8 y14 addr9 u15 v ddint v15 v ddint w15 addr5 y15 addr7 u16 v ddext v16 gnd w16 addr4 y16 addr6 u17 v ddint v17 gnd w17 addr1 y17 addr3 u18 v ddint v18 gnd w18 addr2 y18 gnd u19 data0 v19 data1 w19 addr0 y19 gnd u20 data2 v20 data3 w20 nc y20 nc 1 applies to adsp-21368 models only. table 46. 256-ball sbga pin assignment (n umerically by ball number) (continued) ball no. signal ball no. signal ball no. signal ball no. signal
adsp-21367/adsp-21368/adsp-21369 rev. a | page 51 of 56 | august 2006 figure 43 shows the bottom view of the sbga ball configura- tion. figure 44 shows the top view of the sbga ball configuration. figure 43. 256-ball sbga ball configuration (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t no connect v ddint i/o signals gnd key v ddext a vss a vdd bottom view figure 44. 256-ball sbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t no connect v ddint i/o signals gnd key v ddext a vss a vdd top view
rev. a | page 52 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 208-lead mqfp pinout table 47. 208-lead mqfp pin assignment (numerically by lead number) pin no. signal pin no. signal pin no. signal pin no. signal 1v dd 53 v dd 105 v dd 157 v dd 2 data28 54 gnd 106 gnd 158 v dd 3data27 55v ddext 107 v ddext 159 gnd 4 gnd 56 addr0 108 sdcas 160 v dd 5v ddext 57 addr2 109 sdras 161 v dd 6 data26 58 addr1 110 sdcke 162 v dd 7 data25 59 addr4 111 sdwe 163 tdi 8data24 60addr3 112wr 164 trst 9 data23 61 addr5 113 sda10 165 tck 10 gnd 62 gnd 114 gnd 166 gnd 11 v dd 63 v dd 115 v ddext 167 v dd 12 data22 64 gnd 116 sdclk0 168 tms 13 data21 65 v ddext 117 gnd 169 clk_cfg0 14 data20 66 addr6 118 v dd 170 boot_cfg0 15 v ddext 67 addr7 119 rd 171 clk_cfg1 16 gnd 68 addr8 120 ack 172 emu 17 data19 69 addr9 121 flag3 173 boot_cfg1 18 data18 70 addr10 122 flag2 174 tdo 19 v dd 71 gnd 123 flag1 175 dai4 20 gnd 72 v dd 124 flag0 176 dai2 21 data17 73 gnd 125 dai20 177 dai3 22 v dd 74 v ddext 126 gnd 178 dai1 23 gnd 75 addr11 127 v dd 179 v ddext 24 v dd 76 addr12 128 gnd 180 gnd 25 gnd 77 addr13 129 v ddext 181 v dd 26 data16 78 gnd 130 dai19 182 gnd 27 data15 79 v dd 131 dai18 183 dpi14 28 data14 80 avss 132 dai17 184 dpi13 29 data13 81 avdd 133 dai16 185 dpi12 30 data12 82 gnd 134 dai15 186 dpi11 31 v ddext 83 clkin 135 dai14 187 dpi10 32 gnd 84 xtal2 136 dai13 188 dpi9 33 v dd 85 v ddext 137 dai12 189 dpi8 34 gnd 86 gnd 138 v dd 190 dpi7 35 data11 87 v dd 139 v ddext 191 v ddext 36 data10 88 addr14 140 gnd 192 gnd 37 data9 89 gnd 141 v dd 193 v dd 38 data8 90 v ddext 142 gnd 194 gnd 39 data7 91 addr15 143 dai11 195 dpi6 40 data6 92 addr16 144 dai10 196 dpi5 41 v ddext 93 addr17 145 dai8 197 dpi4 42 gnd 94 addr18 146 dai9 198 dpi3 43 v dd 95 gnd 147 dai6 199 dpi1 44 data4 96 v ddext 148 dai7 200 dpi2
adsp-21367/adsp-21368/adsp-21369 rev. a | page 53 of 56 | august 2006 45 data5 97 addr19 149 dai5 201 clkout 46 data2 98 addr20 150 v ddext 202 reset 47 data3 99 addr21 151 gnd 203 v ddext 48 data0 100 addr23 152 v dd 204 gnd 49 data1 101 addr22 153 gnd 205 data30 50 v ddext 102 ms1 154 v dd 206 data31 51 gnd 103 ms0 155 gnd 207 data29 52 v dd 104 v dd 156 v dd 208 v dd table 47. 208-lead mqfp pin assignment (num erically by lead number) (continued) pin no. signal pin no. signal pin no. signal pin no. signal
rev. a | page 54 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 package dimensions the adsp-21367/adsp-21368/adsp -21369 processors are available in 256-ball lead-free and leaded sbga, and 208-lead lead-free mqfp packages. figure 45. 208-lea d mqfp (s-208-2) 0.20 0.09 3.60 3.40 3.20 0.50 0.25 0.08 max (lead coplanarity) view a rotated 90 ccw 1 208 157 156 105 104 53 52 top view (pins down) 0.50 bsc 28.20 28.00 sq 27.80 0.27 0.17 (lead pitch) (lead width) seating plane 4.10 max 0.75 0.60 0.45 notes: 1. the actual position of each lead is within 0.08 from its ideal position when measured in the lateral direction. 2. center dimensions are nominal. 3. dimensions are in millimeters and comply with jedec standard ms-029, fa-1. view a pin 1 indicator 30.85 30.60 sq 30.35
adsp-21367/adsp-21368/adsp-21369 rev. a | page 55 of 56 | august 2006 surface-mount design table 48 is provided as an aide to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . figure 46. 256-ball sbga, thermally enhanced (bp-256) 1.27 nom 1.70 max 0.90 0.75 0.60 ball diameter 0.70 0.60 0.50 1.00 0.80 0.60 0.10 min seating plane 0.20 coplanarity 0.25 min 4 top view a1 ball indicator dimensions are in millimeters and comply with jedec standards mo-192-bal-2. 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t bottom view 27.00 bsc sq 24.13 ref sq a1 corner index area detail a detail a table 48. sbga data for use with surface-mount design package ball attach type solder mask opening ball pad size 256-lead ball grid array sbga (bp-256) solder mask defined (smd) 0.63 0.73
rev. a | page 56 of 56 | august 2006 adsp-21367/adsp-21368/adsp-21369 ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05267-0-8/06(a) ordering guide part number temperature range 1 1 referenced temperature is ambient temperature. instruction rate on-chip sram rom operating voltage internal/external package description package option adsp-21367ksz-1a 2, 3 2 z = pb-free part. 3 available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. fo r a complete list, visit our website at www.analog.com/sharc. 0 c to +70 c 266 mhz 2m bit 6m bit 1.2 v/3.3 v 208-lead mqfp s-208-2 adsp-21367kbp-2a 3 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21367kbpz-2a 2, 3 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21367bbp-2a C40 c to +85 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21367bbpz-2a 2 C40 c to +85 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21368kbp-2a 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 ADSP-21368KBPZ-2A 2 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21368bbp-2a C40 c to +85 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21368bbpz-2a 2 C40 c to +85 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21369ksz-1a 2 0 c to +70 c 266 mhz 2m bit 6m bit 1.2 v/3.3 v 208-lead mqfp s-208-2 adsp-21369kbp-2a 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21369kbpz-2a 2 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21369bbp-2a C40 c to +85 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 adsp-21369bbpz-2a 2 C40 c to +85 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256

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